Executive Summary: Analog In-Memory Computing (AIMC)

This structured literature review establishes the crucial role of Analog In-Memory Computing (AIMC) as the leading architectural solution to overcome the fundamental von Neumann bottleneck that limits the performance and energy efficiency of modern Artificial Intelligence (AI) hardware.

AIMC integrates computation directly within non-volatile memory (NVM) arrays, leveraging the physical properties of devices like Resistive RAM (RRAM) and Phase-Change Memory (PCM) to perform massively parallel Matrix-Vector Multiplication (MVM) in the analog domain.

Theme	Key Findings & Expert Insights
Historical Evolution	The field’s progression is defined by material science, beginning with Leon Chua’s 1971 memristor theory and accelerating dramatically after the 2008 realization of the memristor. The evolution has shifted from conceptual frameworks to practical integration of NVM arrays as computational crossbar elements.
Pioneering Studies	Recent seminal work demonstrates AIMC’s practical viability. Breakthroughs include the use of 3D AIMC architectures for accelerating dynamic weights in complex Transformer and Mixture-of-Experts (MoE) models [Bu¨chel et al., 2025] and the development of memristor-based nonlinear sorting systems for data-intensive processing [Yuchao et al., 2025]. These studies validate AIMC’s potential for high-efficiency AI acceleration.
Ongoing Debates & Challenges	The core debate centers on the precision-efficiency trade-off. While analog computation offers superior power efficiency and parallelism, it inherently suffers from device non-idealities (e.g., programming variability, noise, limited endurance) when compared to digital precision. Manufacturing challenges related to high-yield, large-scale 3D integration remain a significant hurdle.
Gaps & Future Directions	Future research must prioritize the development of hybrid digital-analog architectures to mitigate analog inaccuracies while maintaining efficiency. Critical gaps include creating robust hardware-aware training toolchains and programming models, as well as advancing thermal and power management solutions for dense 3D AIMC chips. The next phase of AIMC development requires a holistic, co-design approach involving device physics, circuit design, and machine learning algorithms.

AIMC represents not merely an incremental improvement but a paradigm shift, positioning it as the indispensable backbone for sustainable, high-performance computing at the edge and in the data center.